I. Field
The present disclosure relates generally to electronics, and more specifically to a memory device.
II. Background
Memory devices are commonly used in many electronics devices such as computers, wireless communication devices, personal digital assistants (PDAs), etc. A memory device typically includes many rows and columns of memory cells. Each memory cell may be loaded with a data value, which may be a binary “0” or “1”. To read a given memory cell in a given row and column, a word line for the row is activated, and the memory cell either charges or discharges a bit line for the column depending on the data value stored in the memory cell. A sense amplifier detects the voltage on the bit line and provides a logic value based on the detected voltage.
The sense amplifier should be turned on as early as possible and for a minimum amount of time in order to achieve high operating speed and low power consumption. The sense amplifier may be activated after the bit line has been sufficiently charged or discharged so that the data value stored in the memory cell can be reliably detected. This charge/discharge time is dependent on transistor characteristics and parasitic effects, which may vary widely due to integrated circuit (IC) process, temperature, and power supply variations. Process variation is more severe as IC fabrication technology improves and transistor size shrinks. The amount of time allocated for charging and discharging the bit line may be selected based on the worst-case process variation in order to ensure that the bit line is sufficiently charged or discharged prior to sensing. However, designing for the worst-case process variation may reduce operating speed and/or increase power consumption.
There is therefore a need in the art for a memory device that can efficiently account for process and other variations.